diff --git a/targets/stm32l442/Makefile b/targets/stm32l442/Makefile
index e8f209c..54209d2 100644
--- a/targets/stm32l442/Makefile
+++ b/targets/stm32l442/Makefile
@@ -73,9 +73,9 @@ clean:
 flash: $(TARGET).hex
 	STM32_Programmer_CLI -c port=SWD -halt -e all --readunprotect
 	STM32_Programmer_CLI -c port=SWD -halt  -d $(TARGET).hex -rst
-	STM32_Programmer_CLI -c port=SWD  -rst
-	sleep 0.5
-	python dfuse-tool/dfuse-tool.py --leave
+
+detach:
+	STM32_Programmer_CLI -c port=usb1 -ob nBOOT0=1
 
 cbor:
 	cd ../../tinycbor/ && make clean
diff --git a/targets/stm32l442/src/flash.c b/targets/stm32l442/src/flash.c
index 1b09d66..fafe136 100644
--- a/targets/stm32l442/src/flash.c
+++ b/targets/stm32l442/src/flash.c
@@ -25,10 +25,12 @@ void flash_option_bytes_init(int boot_from_dfu)
 #else
     uint32_t val = 0xfffff8b9;
 #endif
-    if (!boot_from_dfu)
+
+    if (boot_from_dfu)
     {
-        val &= ~(1<<26); // nSWBOOT0 = 0  (boot from nBoot0)
+        val &= ~(1<<27); // nBOOT0 = 0  (boot from system rom)
     }
+    val &= ~(1<<26); // nSWBOOT0 = 0  (boot from nBoot0)
     val &= ~(1<<25); // SRAM2_RST = 1 (erase sram on reset)
     val &= ~(1<<24); // SRAM2_PE = 1 (parity check en)