From 44077a4f2f7c2b3857507853f51a616fdae9dcce Mon Sep 17 00:00:00 2001 From: Conor Patrick Date: Sun, 6 Jan 2019 17:12:26 -0500 Subject: [PATCH] spi interface WORKS --- targets/stm32l432/src/device.c | 182 +++++++++++++++++++++++++++++++++ targets/stm32l432/src/init.c | 74 ++++++++------ 2 files changed, 223 insertions(+), 33 deletions(-) diff --git a/targets/stm32l432/src/device.c b/targets/stm32l432/src/device.c index 7bc5f48..60e0b76 100644 --- a/targets/stm32l432/src/device.c +++ b/targets/stm32l432/src/device.c @@ -25,6 +25,7 @@ #include "stm32l4xx_ll_gpio.h" #include "stm32l4xx_ll_tim.h" #include "stm32l4xx_ll_usart.h" +#include "stm32l4xx_ll_spi.h" #include "usbd_hid.h" #include APP_CONFIG @@ -369,6 +370,141 @@ uint32_t ctap_atomic_count(int sel) return lastc; } +static void flush_rx() +{ + while(LL_SPI_IsActiveFlag_RXNE(SPI1) != 0) + { + LL_SPI_ReceiveData8(SPI1); + } +} +static void wait_for_tx() +{ + // while (LL_SPI_IsActiveFlag_BSY(SPI1) == 1) + // ; + while(LL_SPI_GetTxFIFOLevel(SPI1) != LL_SPI_TX_FIFO_EMPTY) + ; +} +static void wait_for_rx() +{ + while(LL_SPI_IsActiveFlag_RXNE(SPI1) == 0) + ; +} + +void ams_write_reg(uint8_t addr, uint8_t tx) +{ + LL_GPIO_ResetOutputPin(SOLO_AMS_CS_PORT,SOLO_AMS_CS_PIN); + delay(1); + LL_SPI_TransmitData8(SPI1,0x00| addr); + LL_SPI_ReceiveData8(SPI1); + while (LL_SPI_IsActiveFlag_BSY(SPI1) == 1) + ; + LL_SPI_TransmitData8(SPI1,tx); + while (LL_SPI_IsActiveFlag_BSY(SPI1) == 1) + ; + LL_SPI_ReceiveData8(SPI1); + + LL_GPIO_SetOutputPin(SOLO_AMS_CS_PORT,SOLO_AMS_CS_PIN); + // delay(1); + LL_GPIO_ResetOutputPin(SOLO_AMS_CS_PORT,SOLO_AMS_CS_PIN); + +} + +uint8_t send_recv(uint8_t b) +{ + wait_for_tx(); + LL_SPI_TransmitData8(SPI1, b); + wait_for_rx(); + b = LL_SPI_ReceiveData8(SPI1); + return b; +} + +uint8_t send_recv2(uint8_t b1,uint8_t b2) +{ + wait_for_tx(); + LL_SPI_TransmitData8(SPI1, b1); + LL_SPI_TransmitData8(SPI1, b2); + wait_for_tx(); + LL_SPI_ReceiveData8(SPI1); + uint8_t b = LL_SPI_ReceiveData8(SPI1); + return b; +} +#define SELECT() LL_GPIO_ResetOutputPin(SOLO_AMS_CS_PORT,SOLO_AMS_CS_PIN) +#define UNSELECT() LL_GPIO_SetOutputPin(SOLO_AMS_CS_PORT,SOLO_AMS_CS_PIN) +uint8_t ams_read_reg(uint8_t addr) +{ + delay(2); + flush_rx(); + LL_GPIO_ResetOutputPin(SOLO_AMS_CS_PORT,SOLO_AMS_CS_PIN); + delay(2); + + uint8_t data = send_recv2(0x20| (addr & 0x1f), 0); + // send_recv(0x20| addr); + // + // uint8_t data = send_recv(0); + + delay(2); + LL_GPIO_SetOutputPin(SOLO_AMS_CS_PORT,SOLO_AMS_CS_PIN); + delay(2); + return data; +} + +// data must be 14 bytes long +void read_reg_block2(uint8_t * data) +{ + int i; + + for (i = 0; i < 0x20; i++) + { + if (i < 6 || (i >=8 && i < 0x0f) || (i >= 0x1e)) + { + *data = ams_read_reg(i); + data++; + } + } + +} + + +// data must be 14 bytes long +void read_reg_block(uint8_t * data, int count) +{ + int i; + uint8_t mode = 0x20 | (0 ); + flush_rx(); + SELECT(); + delay(2); + send_recv(mode); + for (i = 0; i < count; i++) + { + mode = send_recv(0); + // if (i < 6 || (i >=8 && i < 0x0f) || (i >= 0x1e)) + // { + *data = mode; + data++; + // } + } + + delay(2); + UNSELECT(); + // delay(2); + // SELECT(); +} + +void ams_write_command(uint8_t cmd) +{ + + uint8_t mode = cmd; + // delay(10); + + // delay(10); + SELECT(); + delay(1); + send_recv(mode); + UNSELECT(); + SELECT(); + +} + void device_manage() @@ -391,6 +527,52 @@ void device_manage() } } #endif + + static int run = 0; + + if (!run) + { + uint8_t regs[0x20]; + run = 1; + + LL_GPIO_SetPinMode(SOLO_AMS_CS_PORT,SOLO_AMS_CS_PIN,LL_GPIO_MODE_OUTPUT); + LL_GPIO_SetOutputPin(SOLO_AMS_CS_PORT,SOLO_AMS_CS_PIN); + + LL_SPI_SetClockPolarity(SPI1,LL_SPI_POLARITY_LOW); + LL_SPI_SetClockPhase(SPI1,LL_SPI_PHASE_2EDGE); + LL_SPI_SetRxFIFOThreshold(SPI1,LL_SPI_RX_FIFO_TH_QUARTER); + LL_SPI_Enable(SPI1); + + delay(10); + LL_GPIO_SetOutputPin(SOLO_AMS_CS_PORT,SOLO_AMS_CS_PIN); + delay(10); + // LL_GPIO_ResetOutputPin(SOLO_AMS_CS_PORT,SOLO_AMS_CS_PIN); + delay(10); + // ams_write_command(0xC2); // Set to default state + // ams_write_command(0xC4); // Clear buffer + + int x; + for (x = 0 ; x < 10; x++) + { + flush_rx(); + + + memset(regs,0,sizeof(regs)); + read_reg_block(regs,sizeof(regs)); + printf1(TAG_NFC,"regs: "); dump_hex1(TAG_NFC,regs,sizeof(regs)); + + } + + // + // LL_GPIO_SetOutputPin(SOLO_AMS_CS_PORT,SOLO_AMS_CS_PIN); + // + // memset(regs,0,sizeof(regs)); + // for (x = 0 ; x < sizeof(regs); x++) + // { + // regs[x] = ams_read_reg(x); + // } + // printf1(TAG_NFC,"regs2: "); dump_hex1(TAG_NFC,regs,sizeof(regs)); + } } static int handle_packets() diff --git a/targets/stm32l432/src/init.c b/targets/stm32l432/src/init.c index aa66189..bb65b32 100644 --- a/targets/stm32l432/src/init.c +++ b/targets/stm32l432/src/init.c @@ -85,14 +85,14 @@ void hw_init(void) MX_TIM2_Init(); // PWM for LEDs MX_TIM6_Init(); // ~1 ms timer - MX_SPI1_Init(); + #if DEBUG_LEVEL > 0 MX_USART1_UART_Init();// debug uart #endif MX_RNG_Init(); - + MX_SPI1_Init(); TIM6->SR = 0; __enable_irq(); NVIC_EnableIRQ(TIM6_IRQn); @@ -145,8 +145,15 @@ void SystemClock_Config(void) { } - LL_RCC_MSI_Enable(); + LL_RCC_LSI_Enable(); + + /* Wait till LSI is ready */ + while(LL_RCC_LSI_IsReady() != 1) + { + + } + LL_RCC_MSI_Enable(); /* Wait till MSI is ready */ while(LL_RCC_MSI_IsReady() != 1) { @@ -424,41 +431,42 @@ static void MX_RNG_Init(void) static void MX_SPI1_Init(void) { - LL_SPI_InitTypeDef SPI_InitStruct; + LL_SPI_InitTypeDef SPI_InitStruct; - LL_GPIO_InitTypeDef GPIO_InitStruct; + LL_GPIO_InitTypeDef GPIO_InitStruct; - /* Peripheral clock enable */ - LL_APB2_GRP1_EnableClock(LL_APB2_GRP1_PERIPH_SPI1); + /* Peripheral clock enable */ + LL_APB2_GRP1_EnableClock(LL_APB2_GRP1_PERIPH_SPI1); - /**SPI1 GPIO Configuration - PA5 ------> SPI1_SCK - PA6 ------> SPI1_MISO - PA7 ------> SPI1_MOSI - */ - GPIO_InitStruct.Pin = LL_GPIO_PIN_5|LL_GPIO_PIN_6|LL_GPIO_PIN_7; - GPIO_InitStruct.Mode = LL_GPIO_MODE_ALTERNATE; - GPIO_InitStruct.Speed = LL_GPIO_SPEED_FREQ_VERY_HIGH; - GPIO_InitStruct.OutputType = LL_GPIO_OUTPUT_PUSHPULL; - GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; - GPIO_InitStruct.Alternate = LL_GPIO_AF_5; - LL_GPIO_Init(GPIOA, &GPIO_InitStruct); + /**SPI1 GPIO Configuration + PA5 ------> SPI1_SCK + PA6 ------> SPI1_MISO + PA7 ------> SPI1_MOSI + */ + GPIO_InitStruct.Pin = LL_GPIO_PIN_5|LL_GPIO_PIN_6|LL_GPIO_PIN_7; + GPIO_InitStruct.Mode = LL_GPIO_MODE_ALTERNATE; + GPIO_InitStruct.Speed = LL_GPIO_SPEED_FREQ_VERY_HIGH; + GPIO_InitStruct.OutputType = LL_GPIO_OUTPUT_PUSHPULL; + GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; + GPIO_InitStruct.Alternate = LL_GPIO_AF_5; + LL_GPIO_Init(GPIOA, &GPIO_InitStruct); - /* SPI1 parameter configuration*/ - SPI_InitStruct.TransferDirection = LL_SPI_FULL_DUPLEX; - SPI_InitStruct.Mode = LL_SPI_MODE_MASTER; - SPI_InitStruct.DataWidth = LL_SPI_DATAWIDTH_8BIT; - SPI_InitStruct.ClockPolarity = LL_SPI_POLARITY_LOW; - SPI_InitStruct.ClockPhase = LL_SPI_PHASE_1EDGE; - SPI_InitStruct.NSS = LL_SPI_NSS_SOFT; - SPI_InitStruct.BaudRate = LL_SPI_BAUDRATEPRESCALER_DIV64; - SPI_InitStruct.BitOrder = LL_SPI_MSB_FIRST; - SPI_InitStruct.CRCCalculation = LL_SPI_CRCCALCULATION_DISABLE; - SPI_InitStruct.CRCPoly = 7; - LL_SPI_Init(SPI1, &SPI_InitStruct); + /* SPI1 parameter configuration*/ + SPI_InitStruct.TransferDirection = LL_SPI_FULL_DUPLEX; + SPI_InitStruct.Mode = LL_SPI_MODE_MASTER; + SPI_InitStruct.DataWidth = LL_SPI_DATAWIDTH_8BIT; + SPI_InitStruct.ClockPolarity = LL_SPI_POLARITY_LOW; + SPI_InitStruct.ClockPhase = LL_SPI_PHASE_2EDGE; + SPI_InitStruct.NSS = LL_SPI_NSS_SOFT; + SPI_InitStruct.BaudRate = LL_SPI_BAUDRATEPRESCALER_DIV64; + SPI_InitStruct.BitOrder = LL_SPI_MSB_FIRST; + SPI_InitStruct.CRCCalculation = LL_SPI_CRCCALCULATION_DISABLE; + SPI_InitStruct.CRCPoly = 7; + LL_SPI_Init(SPI1, &SPI_InitStruct); - LL_SPI_SetStandard(SPI1, LL_SPI_PROTOCOL_MOTOROLA); + LL_SPI_SetStandard(SPI1, LL_SPI_PROTOCOL_MOTOROLA); + + // LL_SPI_EnableNSSPulseMgt(SPI1); - LL_SPI_EnableNSSPulseMgt(SPI1); }