From 9ff5dc63738b101eb23dacd0088ed12bfe7eceda Mon Sep 17 00:00:00 2001 From: Conor Patrick Date: Sun, 2 Dec 2018 20:30:28 -0500 Subject: [PATCH] bug fixes, now it boots application --- fido2/ctap.c | 2 +- fido2/main.c | 11 ++- targets/stm32l442/Makefile | 8 +- targets/stm32l442/bootloader/bootloader.h | 2 +- targets/stm32l442/bootloader/main.c | 68 +++++++------- targets/stm32l442/merge_hex.py | 8 +- targets/stm32l442/src/app.h | 2 +- targets/stm32l442/src/device.c | 4 +- targets/stm32l442/src/init.c | 104 +++++++++------------- targets/stm32l442/src/system_stm32l4xx.c | 6 -- targets/stm32l442/stm32l432xx.ld | 3 +- 11 files changed, 104 insertions(+), 114 deletions(-) diff --git a/fido2/ctap.c b/fido2/ctap.c index 43793e5..f1a4ccd 100644 --- a/fido2/ctap.c +++ b/fido2/ctap.c @@ -1463,7 +1463,7 @@ uint8_t ctap_request(uint8_t * pkt_raw, int length, CTAP_RESPONSE * resp) else { printf2(TAG_ERR, "unwanted GET_NEXT_ASSERTION. lastcmd == 0x%02x\n", getAssertionState.lastcmd); - dump_hex1(TAG_GREEN, &getAssertionState, sizeof(getAssertionState)); + dump_hex1(TAG_GREEN, (uint8_t*)&getAssertionState, sizeof(getAssertionState)); status = CTAP2_ERR_NOT_ALLOWED; } break; diff --git a/fido2/main.c b/fido2/main.c index d864845..2b304ea 100644 --- a/fido2/main.c +++ b/fido2/main.c @@ -61,11 +61,15 @@ int main(int argc, char * argv[]) device_init(); printf1(TAG_GEN,"init device\n"); - printf1(TAG_GEN,"init ctaphid\n"); - ctaphid_init(); + usbhid_init(); + printf1(TAG_GEN,"init usb\n"); + + + ctaphid_init(); + printf1(TAG_GEN,"init ctaphid\n"); - printf1(TAG_GEN,"init ctap\n"); ctap_init(); + printf1(TAG_GEN,"init ctap\n"); memset(hidmsg,0,sizeof(hidmsg)); @@ -76,7 +80,6 @@ int main(int argc, char * argv[]) { if (millis() - t1 > 100) { - /*printf1(TAG_GEN,"heartbeat %ld\n", beat++);*/ heartbeat(); t1 = millis(); } diff --git a/targets/stm32l442/Makefile b/targets/stm32l442/Makefile index 940d00c..54dfb0a 100644 --- a/targets/stm32l442/Makefile +++ b/targets/stm32l442/Makefile @@ -42,7 +42,7 @@ CHIP=STM32L442xx DEFINES = -D$(CHIP) -DAES256=1 -DUSE_FULL_LL_DRIVER -DAPP_CONFIG=\"app.h\" # DEFINES += -DTEST_SOLO_STM32 -DTEST -DTEST_FIFO=1 -CFLAGS=$(INC) -c $(DEFINES) -Wall -fdata-sections -ffunction-sections $(HW) +CFLAGS=$(INC) -c $(DEFINES) -Wall -fdata-sections -ffunction-sections $(HW) -g LDFLAGS_LIB=$(HW) $(SEARCH) -specs=nano.specs -specs=nosys.specs -Wl,--gc-sections -u _printf_float -lnosys LDFLAGS=$(HW) $(LDFLAGS_LIB) -T$(LDSCRIPT) -Wl,-Map=$(TARGET).map,--cref -ltinycbor @@ -68,7 +68,7 @@ all: $(TARGET).elf $(CP) -O ihex $^ $(TARGET).hex bootloader: - make -f bootloader.mk + $(MAKE) -f bootloader.mk clean: rm -f *.o src/*.o src/*.elf bootloader/*.o $(OBJ) @@ -78,7 +78,9 @@ flash: $(TARGET).hex STM32_Programmer_CLI -c port=SWD -halt -d $(TARGET).hex -rst flashall: - # STM32_Programmer_CLI -c port=SWD -halt -e all --readunprotect + #$(MAKE) -f bootloader.mk -j8 + python .\merge_hex.py .\solo.hex .\bootloader.hex all.hex + STM32_Programmer_CLI -c port=SWD -halt -e all --readunprotect STM32_Programmer_CLI -c port=SWD -halt -d all.hex -rst detach: diff --git a/targets/stm32l442/bootloader/bootloader.h b/targets/stm32l442/bootloader/bootloader.h index bfd78aa..2f4c41b 100644 --- a/targets/stm32l442/bootloader/bootloader.h +++ b/targets/stm32l442/bootloader/bootloader.h @@ -16,7 +16,7 @@ #define ENABLE_U2F_EXTENSIONS // #define ENABLE_U2F -#define APPLICATION_JUMP_ADDR (0x08000000 + 32 * 2048) +#define APPLICATION_JUMP_ADDR (0x08000000 + 32 * 1024) #define DISABLE_CTAPHID_PING #define DISABLE_CTAPHID_WINK diff --git a/targets/stm32l442/bootloader/main.c b/targets/stm32l442/bootloader/main.c index 24b6af1..0040d07 100644 --- a/targets/stm32l442/bootloader/main.c +++ b/targets/stm32l442/bootloader/main.c @@ -37,46 +37,52 @@ uint8_t REBOOT_FLAG = 0; -#if defined ( __CC_ARM ) -__asm void BOOT_jump(uint32_t sp, uint32_t pc) + + +// void __attribute__((optimize("O0"))) BOOT_boot(void) +void BOOT_boot(void) { - /* Set new MSP, PSP based on SP (r0)*/ - msr msp, r0 - msr psp, r0 - - /* Jump to PC (r1)*/ - bx r1 -} -#else -void __attribute__((optimize("O0"))) BOOT_jump(uint32_t sp, uint32_t pc) -{ - (void) sp; - (void) pc; - /* Set new MSP, PSP based on SP (r0)*/ - __asm("msr msp, r0"); - __asm("msr psp, r0"); - - /* Jump to PC (r1)*/ - __asm("mov pc, r1"); -} -#endif + uint32_t sp; + typedef void (*pFunction)(void); + pFunction jump; -void __attribute__((optimize("O0"))) BOOT_boot(void) -{ - uint32_t pc, sp; + /* Reset the RCC clock configuration to the default reset state ------------*/ + /* Set MSION bit */ + RCC->CR |= RCC_CR_MSION; + + /* Reset CFGR register */ + RCC->CFGR = 0x00000000U; + + /* Reset HSEON, CSSON , HSION, and PLLON bits */ + RCC->CR &= 0xEAF6FFFFU; + + /* Reset PLLCFGR register */ + RCC->PLLCFGR = 0x00001000U; + + /* Reset HSEBYP bit */ + RCC->CR &= 0xFFFBFFFFU; + + /* Disable all interrupts */ + RCC->CIER = 0x00000000U; + uint32_t *bootAddress = (uint32_t *)(APPLICATION_JUMP_ADDR); + printf("stack addr: %02lx\r\n",bootAddress[0]); + printf("jmp addr: %02lx\r\n",bootAddress[1]); + /* Set new vector table */ - SCB->VTOR = (uint32_t)bootAddress; + SCB->VTOR = APPLICATION_JUMP_ADDR; /* Read new SP and PC from vector table */ sp = bootAddress[0]; - pc = bootAddress[1]; + jump = (pFunction)bootAddress[1]; /* Do a jump by loading the PC and SP into the CPU registers */ - BOOT_jump(sp, pc); + __set_MSP(sp); + jump(); + //jmp(); } int main(int argc, char * argv[]) @@ -126,9 +132,11 @@ int main(int argc, char * argv[]) printf1(TAG_RED,"Not authorized to boot\r\n"); } - printf1(TAG_GEN,"init ctaphid\n"); + usbhid_init(); + printf1(TAG_GEN,"init usb\n"); + ctaphid_init(); - + printf1(TAG_GEN,"init ctaphid\n"); memset(hidmsg,0,sizeof(hidmsg)); diff --git a/targets/stm32l442/merge_hex.py b/targets/stm32l442/merge_hex.py index 5bf5522..79efedc 100644 --- a/targets/stm32l442/merge_hex.py +++ b/targets/stm32l442/merge_hex.py @@ -20,9 +20,9 @@ first = IntelHex(sys.argv[1]) for i in range(2, len(sys.argv)-1): first.merge(IntelHex( sys.argv[i] ), overlap = 'replace') -first[AUTH_WORD_ADDR] = 4 -first[AUTH_WORD_ADDR+1] = 5 -first[AUTH_WORD_ADDR+2] = 6 -first[AUTH_WORD_ADDR+3] = 7 +first[AUTH_WORD_ADDR] = 0 +first[AUTH_WORD_ADDR+1] = 0 +first[AUTH_WORD_ADDR+2] = 0 +first[AUTH_WORD_ADDR+3] = 0 first.tofile(sys.argv[len(sys.argv)-1], format='hex') diff --git a/targets/stm32l442/src/app.h b/targets/stm32l442/src/app.h index a05b461..f506427 100644 --- a/targets/stm32l442/src/app.h +++ b/targets/stm32l442/src/app.h @@ -4,7 +4,7 @@ #define DEBUG_UART USART1 -#define DEBUG_LEVEL 0 +#define DEBUG_LEVEL 1 #define NON_BLOCK_PRINTING 0 diff --git a/targets/stm32l442/src/device.c b/targets/stm32l442/src/device.c index 16decc5..e76e90b 100644 --- a/targets/stm32l442/src/device.c +++ b/targets/stm32l442/src/device.c @@ -34,7 +34,7 @@ #define RK_END_PAGE (PAGES - 14 + RK_NUM_PAGES) -#define APPLICATION_START_PAGE (0) +#define APPLICATION_START_PAGE (16) #define APPLICATION_START_ADDR flash_addr(APPLICATION_START_PAGE) #define APPLICATION_END_PAGE ((PAGES - 19)) // 119 is NOT included in application @@ -122,8 +122,8 @@ void usb_init(void); void usbhid_init() { usb_init(); - printf1(TAG_GEN,"hello solo\r\n"); } + int usbhid_recv(uint8_t * msg) { if (fifo_hidmsg_size()) diff --git a/targets/stm32l442/src/init.c b/targets/stm32l442/src/init.c index 8cd2d1c..7cab7bc 100644 --- a/targets/stm32l442/src/init.c +++ b/targets/stm32l442/src/init.c @@ -21,6 +21,7 @@ #include "usbd_desc.h" #include "usbd_hid.h" #include "device.h" +#include APP_CONFIG /* USER CODE BEGIN Includes */ @@ -45,79 +46,54 @@ void _Error_Handler(char *file, int line); void hw_init(void) { - /* USER CODE BEGIN 1 */ +#ifdef IS_BOOTLOADER + SCB->VTOR = FLASH_BASE; +#else +#endif + LL_Init(); - /* USER CODE END 1 */ + SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_PWREN); - /* MCU Configuration----------------------------------------------------------*/ - /* Reset of all peripherals, Initializes the Flash interface and the Systick. */ - /* Reset of all peripherals, Initializes the Flash interface and the Systick. */ - LL_Init(); + SystemClock_Config(); // TODO bootloader should not change clk freq. - // enable power clock - SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_PWREN); + MX_GPIO_Init(); + MX_TIM2_Init(); // PWM for LEDs - // enable USB power - SET_BIT(PWR->CR2, PWR_CR2_USV); + MX_TIM6_Init(); // ~1 ms timer - // Enable USB Clock - SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USBFSEN); +#if DEBUG_LEVEL > 0 + MX_USART1_UART_Init();// debug uart +#endif + MX_RNG_Init(); - /* USER CODE BEGIN Init */ - - /* USER CODE END Init */ - - /* Configure the system clock */ - SystemClock_Config(); - - /* USER CODE BEGIN SysInit */ - - /* USER CODE END SysInit */ - - /* Initialize all configured peripherals */ - MX_GPIO_Init(); - MX_TIM2_Init(); - - MX_TIM6_Init(); - #ifndef TEST_SOLO_STM32 - MX_USART1_UART_Init(); - - MX_RNG_Init(); - #endif - - TIM6->SR = 0; - __enable_irq(); - NVIC_EnableIRQ(TIM6_IRQn); -#ifndef TEST_SOLO_STM32 - - #endif - + TIM6->SR = 0; + __enable_irq(); + NVIC_EnableIRQ(TIM6_IRQn); } + static void LL_Init(void) { + LL_APB2_GRP1_EnableClock(LL_APB2_GRP1_PERIPH_SYSCFG); + LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_PWR); + NVIC_SetPriorityGrouping(4); - LL_APB2_GRP1_EnableClock(LL_APB2_GRP1_PERIPH_SYSCFG); - LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_PWR); - - NVIC_SetPriorityGrouping(4); - - /* System interrupt init*/ - /* MemoryManagement_IRQn interrupt configuration */ - NVIC_SetPriority(MemoryManagement_IRQn, NVIC_EncodePriority(NVIC_GetPriorityGrouping(),0, 0)); - /* BusFault_IRQn interrupt configuration */ - NVIC_SetPriority(BusFault_IRQn, NVIC_EncodePriority(NVIC_GetPriorityGrouping(),0, 0)); - /* UsageFault_IRQn interrupt configuration */ - NVIC_SetPriority(UsageFault_IRQn, NVIC_EncodePriority(NVIC_GetPriorityGrouping(),0, 0)); - /* SVCall_IRQn interrupt configuration */ - NVIC_SetPriority(SVCall_IRQn, NVIC_EncodePriority(NVIC_GetPriorityGrouping(),0, 0)); - /* DebugMonitor_IRQn interrupt configuration */ - NVIC_SetPriority(DebugMonitor_IRQn, NVIC_EncodePriority(NVIC_GetPriorityGrouping(),0, 0)); - /* PendSV_IRQn interrupt configuration */ - NVIC_SetPriority(PendSV_IRQn, NVIC_EncodePriority(NVIC_GetPriorityGrouping(),0, 0)); - /* SysTick_IRQn interrupt configuration */ - NVIC_SetPriority(SysTick_IRQn, NVIC_EncodePriority(NVIC_GetPriorityGrouping(),0, 0)); + /* System interrupt init*/ + /* MemoryManagement_IRQn interrupt configuration */ + NVIC_SetPriority(MemoryManagement_IRQn, NVIC_EncodePriority(NVIC_GetPriorityGrouping(),0, 0)); + /* BusFault_IRQn interrupt configuration */ + NVIC_SetPriority(BusFault_IRQn, NVIC_EncodePriority(NVIC_GetPriorityGrouping(),0, 0)); + /* UsageFault_IRQn interrupt configuration */ + NVIC_SetPriority(UsageFault_IRQn, NVIC_EncodePriority(NVIC_GetPriorityGrouping(),0, 0)); + /* SVCall_IRQn interrupt configuration */ + NVIC_SetPriority(SVCall_IRQn, NVIC_EncodePriority(NVIC_GetPriorityGrouping(),0, 0)); + /* DebugMonitor_IRQn interrupt configuration */ + NVIC_SetPriority(DebugMonitor_IRQn, NVIC_EncodePriority(NVIC_GetPriorityGrouping(),0, 0)); + /* PendSV_IRQn interrupt configuration */ + NVIC_SetPriority(PendSV_IRQn, NVIC_EncodePriority(NVIC_GetPriorityGrouping(),0, 0)); + /* SysTick_IRQn interrupt configuration */ + NVIC_SetPriority(SysTick_IRQn, NVIC_EncodePriority(NVIC_GetPriorityGrouping(),0, 0)); } @@ -203,6 +179,12 @@ void SystemClock_Config(void) void usb_init() { + // enable USB power + SET_BIT(PWR->CR2, PWR_CR2_USV); + + // Enable USB Clock + SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USBFSEN); + USBD_Init(&Solo_USBD_Device, &Solo_Desc, 0); USBD_RegisterClass(&Solo_USBD_Device, &USBD_HID); USBD_Start(&Solo_USBD_Device); diff --git a/targets/stm32l442/src/system_stm32l4xx.c b/targets/stm32l442/src/system_stm32l4xx.c index c76fe45..44f5432 100644 --- a/targets/stm32l442/src/system_stm32l4xx.c +++ b/targets/stm32l442/src/system_stm32l4xx.c @@ -219,12 +219,6 @@ void SystemInit(void) /* Disable all interrupts */ RCC->CIER = 0x00000000U; - /* Configure the Vector Table location add offset address ------------------*/ -#ifdef VECT_TAB_SRAM - SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */ -#else - SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */ -#endif } /** diff --git a/targets/stm32l442/stm32l432xx.ld b/targets/stm32l442/stm32l432xx.ld index cbefde8..be6d0ab 100644 --- a/targets/stm32l442/stm32l432xx.ld +++ b/targets/stm32l442/stm32l432xx.ld @@ -42,7 +42,8 @@ _Min_Stack_Size = 0x400; /* required amount of stack */ MEMORY { /* First 32 KB is bootloader */ -FLASH (rx) : ORIGIN = 0x08010000, LENGTH = 206K-8 /* Leave out 18 Kb at end for data */ +/*FLASH (rx) : ORIGIN = 0x08000000, LENGTH = 238K-8 [> Leave out 18 Kb at end for data <]*/ +FLASH (rx) : ORIGIN = 0x08008000, LENGTH = 206K-8 /* Leave out 18 Kb at end for data */ RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 48K SRAM2 (rw) : ORIGIN = 0x10000000, LENGTH = 16K }