move things around and add efm8 and efm32 builds
This commit is contained in:
Conor Patrick
317
efm32/CMSIS/EFM32PG1B/startup_gcc_efm32pg1b.s
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317
efm32/CMSIS/EFM32PG1B/startup_gcc_efm32pg1b.s
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/* @file startup_efm32pg1b.S
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* @brief startup file for Silicon Labs EFM32PG1B devices.
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* For use with GCC for ARM Embedded Processors
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* @version 5.2.2
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* Date: 12 June 2014
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*
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*/
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/* Copyright (c) 2011 - 2014 ARM LIMITED
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All rights reserved.
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Redistribution and use in source and binary forms, with or without
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modification, are permitted provided that the following conditions are met:
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- Redistributions of source code must retain the above copyright
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notice, this list of conditions and the following disclaimer.
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- Redistributions in binary form must reproduce the above copyright
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notice, this list of conditions and the following disclaimer in the
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documentation and/or other materials provided with the distribution.
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- Neither the name of ARM nor the names of its contributors may be used
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to endorse or promote products derived from this software without
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specific prior written permission.
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*
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THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
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LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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POSSIBILITY OF SUCH DAMAGE.
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---------------------------------------------------------------------------*/
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.syntax unified
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.arch armv7-m
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.section .stack
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.align 3
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#ifdef __STACK_SIZE
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.equ Stack_Size, __STACK_SIZE
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#else
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.equ Stack_Size, 0x00000400
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#endif
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.globl __StackTop
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.globl __StackLimit
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__StackLimit:
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.space Stack_Size
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.size __StackLimit, . - __StackLimit
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__StackTop:
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.size __StackTop, . - __StackTop
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.section .heap
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.align 3
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#ifdef __HEAP_SIZE
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.equ Heap_Size, __HEAP_SIZE
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#else
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.equ Heap_Size, 0x00000C00
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#endif
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.globl __HeapBase
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.globl __HeapLimit
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__HeapBase:
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.if Heap_Size
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.space Heap_Size
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.endif
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.size __HeapBase, . - __HeapBase
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__HeapLimit:
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.size __HeapLimit, . - __HeapLimit
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.section .vectors
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.align 2
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.globl __Vectors
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__Vectors:
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.long __StackTop /* Top of Stack */
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.long Reset_Handler /* Reset Handler */
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.long NMI_Handler /* NMI Handler */
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.long HardFault_Handler /* Hard Fault Handler */
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.long MemManage_Handler /* MPU Fault Handler */
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.long BusFault_Handler /* Bus Fault Handler */
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.long UsageFault_Handler /* Usage Fault Handler */
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.long Default_Handler /* Reserved */
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.long Default_Handler /* Reserved */
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.long Default_Handler /* Reserved */
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.long Default_Handler /* Reserved */
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.long SVC_Handler /* SVCall Handler */
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.long DebugMon_Handler /* Debug Monitor Handler */
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.long Default_Handler /* Reserved */
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.long PendSV_Handler /* PendSV Handler */
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.long SysTick_Handler /* SysTick Handler */
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/* External interrupts */
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.long EMU_IRQHandler /* 0 - EMU */
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.long Default_Handler /* 1 - Reserved */
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.long WDOG0_IRQHandler /* 2 - WDOG0 */
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.long Default_Handler /* 3 - Reserved */
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.long Default_Handler /* 4 - Reserved */
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.long Default_Handler /* 5 - Reserved */
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.long Default_Handler /* 6 - Reserved */
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.long Default_Handler /* 7 - Reserved */
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.long LDMA_IRQHandler /* 8 - LDMA */
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.long GPIO_EVEN_IRQHandler /* 9 - GPIO_EVEN */
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.long TIMER0_IRQHandler /* 10 - TIMER0 */
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.long USART0_RX_IRQHandler /* 11 - USART0_RX */
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.long USART0_TX_IRQHandler /* 12 - USART0_TX */
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.long ACMP0_IRQHandler /* 13 - ACMP0 */
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.long ADC0_IRQHandler /* 14 - ADC0 */
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.long IDAC0_IRQHandler /* 15 - IDAC0 */
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.long I2C0_IRQHandler /* 16 - I2C0 */
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.long GPIO_ODD_IRQHandler /* 17 - GPIO_ODD */
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.long TIMER1_IRQHandler /* 18 - TIMER1 */
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.long USART1_RX_IRQHandler /* 19 - USART1_RX */
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.long USART1_TX_IRQHandler /* 20 - USART1_TX */
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.long LEUART0_IRQHandler /* 21 - LEUART0 */
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.long PCNT0_IRQHandler /* 22 - PCNT0 */
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.long CMU_IRQHandler /* 23 - CMU */
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.long MSC_IRQHandler /* 24 - MSC */
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.long CRYPTO_IRQHandler /* 25 - CRYPTO */
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.long LETIMER0_IRQHandler /* 26 - LETIMER0 */
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.long Default_Handler /* 27 - Reserved */
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.long Default_Handler /* 28 - Reserved */
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.long RTCC_IRQHandler /* 29 - RTCC */
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.long Default_Handler /* 30 - Reserved */
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.long CRYOTIMER_IRQHandler /* 31 - CRYOTIMER */
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.long Default_Handler /* 32 - Reserved */
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.long FPUEH_IRQHandler /* 33 - FPUEH */
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.size __Vectors, . - __Vectors
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.text
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.thumb
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.thumb_func
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.align 2
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.globl Reset_Handler
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.type Reset_Handler, %function
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Reset_Handler:
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#ifndef __NO_SYSTEM_INIT
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ldr r0, =SystemInit
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blx r0
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#endif
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/* Firstly it copies data from read only memory to RAM. There are two schemes
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* to copy. One can copy more than one sections. Another can only copy
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* one section. The former scheme needs more instructions and read-only
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* data to implement than the latter.
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* Macro __STARTUP_COPY_MULTIPLE is used to choose between two schemes. */
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#ifdef __STARTUP_COPY_MULTIPLE
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/* Multiple sections scheme.
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*
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* Between symbol address __copy_table_start__ and __copy_table_end__,
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* there are array of triplets, each of which specify:
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* offset 0: LMA of start of a section to copy from
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* offset 4: VMA of start of a section to copy to
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* offset 8: size of the section to copy. Must be multiply of 4
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*
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* All addresses must be aligned to 4 bytes boundary.
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*/
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ldr r4, =__copy_table_start__
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ldr r5, =__copy_table_end__
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.L_loop0:
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cmp r4, r5
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bge .L_loop0_done
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ldr r1, [r4]
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ldr r2, [r4, #4]
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ldr r3, [r4, #8]
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.L_loop0_0:
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subs r3, #4
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ittt ge
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ldrge r0, [r1, r3]
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strge r0, [r2, r3]
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bge .L_loop0_0
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adds r4, #12
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b .L_loop0
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.L_loop0_done:
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#else
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/* Single section scheme.
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*
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* The ranges of copy from/to are specified by following symbols
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* __etext: LMA of start of the section to copy from. Usually end of text
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* __data_start__: VMA of start of the section to copy to
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* __data_end__: VMA of end of the section to copy to
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*
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* All addresses must be aligned to 4 bytes boundary.
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*/
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ldr r1, =__etext
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ldr r2, =__data_start__
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ldr r3, =__data_end__
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.L_loop1:
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cmp r2, r3
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ittt lt
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ldrlt r0, [r1], #4
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strlt r0, [r2], #4
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blt .L_loop1
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#endif /*__STARTUP_COPY_MULTIPLE */
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/* This part of work usually is done in C library startup code. Otherwise,
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* define this macro to enable it in this startup.
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*
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* There are two schemes too. One can clear multiple BSS sections. Another
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* can only clear one section. The former is more size expensive than the
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* latter.
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*
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* Define macro __STARTUP_CLEAR_BSS_MULTIPLE to choose the former.
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* Otherwise efine macro __STARTUP_CLEAR_BSS to choose the later.
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*/
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#ifdef __STARTUP_CLEAR_BSS_MULTIPLE
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/* Multiple sections scheme.
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*
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* Between symbol address __zero_table_start__ and __zero_table_end__,
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* there are array of tuples specifying:
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* offset 0: Start of a BSS section
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* offset 4: Size of this BSS section. Must be multiply of 4
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*/
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ldr r3, =__zero_table_start__
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ldr r4, =__zero_table_end__
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.L_loop2:
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cmp r3, r4
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bge .L_loop2_done
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ldr r1, [r3]
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ldr r2, [r3, #4]
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movs r0, 0
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.L_loop2_0:
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subs r2, #4
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itt ge
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strge r0, [r1, r2]
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bge .L_loop2_0
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adds r3, #8
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b .L_loop2
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.L_loop2_done:
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#elif defined (__STARTUP_CLEAR_BSS)
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/* Single BSS section scheme.
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*
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* The BSS section is specified by following symbols
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* __bss_start__: start of the BSS section.
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* __bss_end__: end of the BSS section.
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*
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* Both addresses must be aligned to 4 bytes boundary.
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*/
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ldr r1, =__bss_start__
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ldr r2, =__bss_end__
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movs r0, 0
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.L_loop3:
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cmp r1, r2
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itt lt
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strlt r0, [r1], #4
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blt .L_loop3
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#endif /* __STARTUP_CLEAR_BSS_MULTIPLE || __STARTUP_CLEAR_BSS */
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#ifndef __START
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#define __START _start
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#endif
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bl __START
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.pool
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.size Reset_Handler, . - Reset_Handler
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.align 1
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.thumb_func
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.weak Default_Handler
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.type Default_Handler, %function
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Default_Handler:
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b .
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.size Default_Handler, . - Default_Handler
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/* Macro to define default handlers. Default handler
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* will be weak symbol and just dead loops. They can be
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* overwritten by other handlers */
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.macro def_irq_handler handler_name
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.weak \handler_name
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.set \handler_name, Default_Handler
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.endm
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def_irq_handler NMI_Handler
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def_irq_handler HardFault_Handler
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def_irq_handler MemManage_Handler
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def_irq_handler BusFault_Handler
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def_irq_handler UsageFault_Handler
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def_irq_handler SVC_Handler
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def_irq_handler DebugMon_Handler
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def_irq_handler PendSV_Handler
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def_irq_handler SysTick_Handler
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def_irq_handler EMU_IRQHandler
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def_irq_handler WDOG0_IRQHandler
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def_irq_handler LDMA_IRQHandler
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def_irq_handler GPIO_EVEN_IRQHandler
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def_irq_handler TIMER0_IRQHandler
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def_irq_handler USART0_RX_IRQHandler
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def_irq_handler USART0_TX_IRQHandler
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def_irq_handler ACMP0_IRQHandler
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def_irq_handler ADC0_IRQHandler
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def_irq_handler IDAC0_IRQHandler
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def_irq_handler I2C0_IRQHandler
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def_irq_handler GPIO_ODD_IRQHandler
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def_irq_handler TIMER1_IRQHandler
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def_irq_handler USART1_RX_IRQHandler
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def_irq_handler USART1_TX_IRQHandler
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def_irq_handler LEUART0_IRQHandler
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def_irq_handler PCNT0_IRQHandler
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def_irq_handler CMU_IRQHandler
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def_irq_handler MSC_IRQHandler
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def_irq_handler CRYPTO_IRQHandler
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def_irq_handler LETIMER0_IRQHandler
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def_irq_handler RTCC_IRQHandler
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def_irq_handler CRYOTIMER_IRQHandler
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def_irq_handler FPUEH_IRQHandler
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.end
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