21 Commits

Author SHA1 Message Date
Conor Patrick
84740f3d6a changes to make firmware interop on all hw models 2019-05-09 16:01:07 -04:00
Conor Patrick
2b2835b823 initial cap sensing boilerplate 2019-05-08 22:26:57 -04:00
Conor Patrick
246dea8a44 fix clock init by setting flash latency last for low freqs 2019-03-02 20:05:27 -05:00
Conor Patrick
e8d0ad5e7c autodetect passive nfc operation or usb operation 2019-02-26 15:04:23 -05:00
Conor Patrick
ff0d42c8d5 refactor clock rates, fix warnings 2019-02-26 13:56:06 -05:00
Conor Patrick
57930aaa13 fix compilation errors 2019-02-26 13:27:25 -05:00
Conor Patrick
1a6895ca25 merge 2019-02-26 13:10:16 -05:00
Conor Patrick
a195408a11 scale up to 24 MHz only for register 2019-02-26 01:51:07 -05:00
Conor Patrick
54b7f42056 passive operation works as is (refactor needed) 2019-02-26 01:19:35 -05:00
yparitcher
400b37a96a
clean up build: GCC warnings 2019-02-12 18:19:38 -05:00
Conor Patrick
ed676151f1 update license to apache2 + mit 2019-02-12 17:18:17 -05:00
Conor Patrick
13d9885da4 initialize at 16MHz, add 24 and 32 options 2019-02-08 13:08:28 -05:00
Conor Patrick
765d532f82 add low freq clocking options 4,8,16MHz 2019-02-06 17:54:52 -05:00
Conor Patrick
1b5e230d45 merge u2f endian fix 2019-02-02 00:32:36 -05:00
Conor Patrick
4ba57ccc85 refactor init functions 2019-02-02 00:23:01 -05:00
Conor Patrick
302ce75ce6 responds to RATS correctly 2019-01-12 20:20:47 -05:00
Conor Patrick
20f8aac768 option to boot at 4MHz with no USB 2019-01-12 16:19:44 -05:00
Conor Patrick
e7f01f4e55 disable CDC ACM when not debugging 2019-01-08 21:18:18 -05:00
Conor Patrick
44077a4f2f spi interface WORKS 2019-01-06 17:12:26 -05:00
Conor Patrick
4c6f0969c1 add spi 2019-01-05 20:58:39 -05:00
Nicolas Stalder
5f3c50e690 we use l432, not l442 2019-01-05 01:44:53 +01:00